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ADNS-2051
Optical Mouse Sensor
Data Sheet
Description
The ADNS-2051 is a low cost optical sensor used to implement a non-mechanical tracking engine for computer mice. It is based on optical navigation technology, which measures changes in position by optically acquiring sequential surface images (frames) and mathematically determining the direction and magnitude of movement. The sensor is housed in a 16-pin staggered dual inline package (DIP) that is designed for use with the HDNS2100 Lens and HDNS-2200 Clip and HLMP-ED80-XX000 (639 nm LED illuminator source). There are no moving parts, and precision optical alignment is not required, facilitating high volume assembly. The output format is two channel quadrature (X and Y direction) which emulates encoder photo-transistors. The current X and Y information are also available in registers accessed via a serial port. Default resolution is specified as 400 counts per inch (cpi), with rates of motion up to 14 inches per second (ips). Resolution can also be programmed to 800 cpi. The part is programmed via a two wire serial port, through registers.
Features
* * * * * * * * * * * * * * * * * * Precise optical navigation technology No mechanical moving parts Complete 2D motion sensor Serial interface and/or quadrature interface Smooth surface navigation Programmable frame speed up to 2300 frames per sec (fps) Accurate motion up to 14 ips 800 cpi resolution High reliability High speed motion detector No precision optical alignment Wave solderable Single 5.0 volt power supply Shutdown pin for USB suspend mode operation Power conservation mode during times of no movement On chip LED drive with regulated current Serial port registers - Programming - Data transfer 16-pin staggered dual inline package (DIP)
Theory of Operation
The ADNS-2051 is based on Optical Navigation Technology. It contains an Image Acquisition System (IAS), a Digital Signal Processor (DSP), a two-channel quadrature output, and a two wire serial port. The IAS acquires microscopic surface images via the lens and illumination system provided by the HDNS-2100, 2200, and HLMP-ED80-XX000 LED. These images are processed by the DSP to determine the direction and distance of motion. The DSP generates the x and y relative displacement values that are converted into two channel quadrature signals.
Applications
* Mice for desktop PCs, workstations, and portable PCs * Trackballs * Integrated input devices
Outline Drawing of ADNS-2051 Optical Mouse Sensor
Pinout
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin SCLK XA XB YB YA XY_LED REFA REFB OSC_IN GND OSC_OUT GND VDD R_BIN PD SDIO Description Serial port clock (input) XA quadrature output XB quadrature output YB quadrature output YA quadrature output LED control Internal reference Internal reference Oscillator input System ground Oscillator output System ground 5.0 volt power supply LED current bin resistor Power down pin, active high Serial data (input and output) Figure 1. Top view
REFB 8 XB YB YA XY_LED REFA 3 13 4 12 5 11 6 10 7 9 OSC_IN GND OSC_OUT GND VDD 16 SCLK XA 1 2 SDIO PD R_BIN
A2051 XYYWWZ
15 14
2
PIN 1
A2051 XYYWWZ
12.85 (AT SHOULDER) (0.506) 22.30 (0.878) 50 0.5 9.10 (0.358) 0.01 (0.000)
*
0.99 (0.039)
2.98 (0.117)
*
3.18 (0.125) 5.16 (0.203)
0.50 CHAMFER LEAD WIDTH 0.50 (0.020) 0.25 (0.010) 1.26 LEAD OFFSET (0.050) 2.54 LEAD PITCH (0.100) * 6.18 (0.243)
0.25 (0.010) 5 3 13.57 0.45 (AT LEAD TIP) (0.534 0.018)
GATE LOCATION SURFACE RECESSED BY 0.3 mm 4.55 (0.179)
6.03 (0.237)
PROTECTIVE KAPTON TAPE 5.00
(MEASURED AT BASE) 5.60 0.03 (0.220 0.001)
GROOVE 7.28 0.03 (0.287 0.001)
(0.002)
* 0.06
1.85 0.03 (0.073 0.001)
A PIN 1 0.80 0.03 CLEAR OPTICAL PATH 13.38 (0.527)
A
*1.5 DRAFT SECTION A-A
1.43 0.03 (0.056 0.001)
2.80 (0.110)
*
NOTES: 1. DIMENSIONS IN MILLIMETERS (INCHES). 2. DIMENSIONAL TOLERANCE: 0.1 mm. 3. COPLANARITY OF LEADS: 0.1 mm. 4. LEAD PITCH TOLERANCE: 0.15 mm. 5. CUMULATIVE PITCH TOLERANCE: 0.15 mm. 6. ANGULAR TOLERANCE: 3.0 DEGREES. 7. MAXIMUM FLASH + 0.2 mm. 8. CHAMFER (25 DEGREES x 2) ON THE TAPER SIDE OF THE LEAD. 9. * THESE DIMENSIONS ARE FOR REFERENCES ONLY AND SHOULD NOT BE USED TO MECHANICALLY REFERENCE THE SENSOR.
Figure 2. Package outline drawing
3
Overview of Optical Mouse Sensor Assembly
2D Assembly Drawing of ADNS-2051 Figures 3 and 4, shown with HDNS-2100, HDNS-2200, and HLMP-ED80-XX000. Avago Technologies provides an IGES file drawing describing the base plate molding features for lens and PCB alignment. The components interlock as they are mounted onto defined features on the base plate. The ADNS-2051 sensor is designed for mounting on a through hole PCB, looking down. There is an aperture stop and features on the package that align to the lens (see Figure 3). The HDNS-2100 lens provides optics for the imaging of the surface as well as illumination of the surface at the optimum angle. Features on the lens align it to the sensor, base plate, and clip with the LED. The lens also has a large round flange to provide a long creepage path for any ESD events that occur at the opening of the base plate (see Figure 4). The HDNS-2200 clip holds the LED in relation to the lens. The LED must be inserted into the clip and the LED's leads formed prior to loading on the PCB. The clip interlocks the sensor to the lens, and through the lens to the alignment features on the base plate. The HLMP-ED80-XX000 LED is recommended for illumination. If used with the bin table, sufficient illumination can be guaranteed.
12.60 (0.498) 11.38 (0.448) 1.27 (0.050) 2.32 (0.091) 40.53 (1.596) 39.39 (1.551) 30.32 (1.194) 3.50 (1.38)
5.10 (0.201)
13.88 (0.546)
0 REF. 1.28 (0.050) CLEAR ZONE 0 REF. 0.80 RECOMMENDED (16 PLACES) (0.031) 7.50 (0.295) 1.22 (0.048)
DIMENSIONS IN MILLIMETERS (INCHES)
Figure 3. Recommended PCB mechanical cutouts and spacing (top view)
ADNS-2051 fig 3
TOP VIEW
44.29 (1.744)
+x
19.10 (0.752)
+y BASE PLATE ESD LENS RING
SIDE VIEW
PLASTIC SPRING CLIP
14.58 (0.574) 10.58 (0.417) 7.45 (0.293) PCB
13.82 (0.544)
SENSOR
BASE PLATE ALIGNMENT POST
DIMENSIONS IN MILLIMETERS (INCHES).
Figure 4. 2D assembly drawing of ADNS-2051 (top and side view)
ADNS-2051 fig 4
4
HDNS-2200 (CLIP)
HLMP-ED80 (LED) ADNS-2051 (SENSOR)
CUSTOMER SUPPLIED PCB
HDNS-2100 (LENS)
CUSTOMER SUPPLIED BASE PLATE WITH RECOMMENDED ALIGNMENT FEATURES PER IGES DRAWING
Figure 5. Exploded view drawing
ADNS-2051 fig 5
PCB Assembly Considerations
1. Insert the sensor and all other electrical components into PCB. 2. Bend the LED leads 90 and then insert the LED into the assembly clip until the snap feature locks the LED base. 3. Insert the LED/clip assembly into PCB. 4. Wave Solder the entire assembly in a no-wash solder process utilizing solder fixture. The solder fixture is needed to protect the sensor during the solder process. The fixture should be designed to expose the sensor leads to solder while shielding the optical aperture from direct solder contact. The solder fixture is also used to set the reference height of the sensor to the PCB top during wave soldering (Note: DO NOT remove the kapton tape during wave soldering). 5. Place the lens onto the base plate.
6. Remove the protective kapton tape from optical aperture of the sensor. Care must be taken to keep contaminants from entering the aperture. It is recommended not to place the PCB facing up during the entire mouse assembly process. The PCB should be held vertically during the kapton removal process. 7. Insert PCB assembly over the lens onto the base plate aligning post to retain PCB assembly. The sensor aperture ring should self-align to the lens. 8. The optical position reference for the PCB is set by the base plate and lens. Note that the PCB motion due to button presses must be minimized to maintain optical alignment. 9. Install mouse top case. There MUST be a feature in the top case to press down onto the clip to ensure all components are interlocked to the correct vertical height.
5
SCLK SERIAL PORT SDIO XA QUADRATURE OUTPUT XB YA YB R_BIN LED XY_LED SERIAL PORT OSCILLATOR
OSC_IN RESONATOR OSC_OUT REFA VOLTAGE REGULATOR AND POWER CONTROL REFB PD VDD GND GND 5 VOLT POWER
POWER ON RESET
VOLTAGE REFERENCE
QUADRATURE OUTPUTS
IMAGE PROCESSOR
LED DRIVE
Figure 6. Block diagram of ADNS-2051 optical mouse sensor
ADNS-2051 fig 6
Design Considerations for Improving ESD Performance
The flange on the lens has been designed to increase the creepage and clearance distance for electrostatic discharge. The table on the right shows typical values assuming base plate construction per the Avago supplied IGES file and HDNS-2100 lens flange. For improved ESD performance, the lens flange can be sealed (i.e. glued) to the base plate. Note that the lens material is polycarbonate and therefore, cyanoacrylatebased adhesives or other adhesives that may damage the lens should NOT be used. The trimmed lens, HDNS-2100#001, is not recommended for corded applications due to the ESD spec requirement.
Typical Distance Creepage Clearance Millimeters 16.0 2.1
SENSOR CLIP PCB LED
LENS/LIGHT PIPE
BASE PLATE
SURFACE
Figure 7. PCB assembly
ADNS-2051 fig 7
6
Recommended Typical Application Using SDIO Pins
0.1 F 11 VDD VPP D+
4.7 F
0.1 F 12 10
13 VDD GND GND
VDD D+ DGND 1.3 k
7 13
INTERNAL IMAGE SENSOR
HDNS-2100 LENS
HLMP-ED80
SURFACE 6 9 18 MHz 11 7 0.1 F REFB R_BIN 8 14 R1 VALUE (k) 15.0 15.0 15.0 15.0 15.0 15.0 ~ 18.0 15.0 ~ 22.0 15.0 ~ 27.0 15.0 ~ 33.0 15.0 ~ 37.0 LED BIN K L M N P Q R S T U 2.2 F
12 D8
CYPRESS CY7C63723A-PC
XY_LED P0.4 18 P0.5 P0.6 P0.7 P0.3 P0.2 17 16 15 4 3 2 1 SCLK 15 16 PD SDIO OSC_IN
VREG
ADNS 2051
CERAMIC RESONATOR MURATA CSALS18M0X53-B0 TDK FCR18.0M2G
GND QA SHLD VDD VDD QB Z-WHEEL ENCODER
5 P1.0 14 P1.1
OSC_OUT REFA
R
L M R BUTTONS XA 2 XB 3 YB 4
1 Z LED
P0.0
P0.1
YA 5
R1
VSS 6 XTALOUT XTALIN
Figure 8. Application using SDIO pins
Notes on Bypass Capacitors:
* Caps for pins 7, 8 and 12, 13 MUST have trace lengths LESS than 5 mm. * The 0.1 F caps must be ceramic. * Caps should have less than 5 nH of self inductance * Caps should have less than 0.2 ESR Surface mount parts are recommended. SDIO and SCLK pins should be grounded if not used.
Regulatory Requirements
* Passes FCC B and worldwide analogous emission limits when assembled into a mouse with unshielded cable and following Avago recommendations. * Passes EN61000-4-4/IEC801-4 EFT tests when assembled into a mouse with unshielded cable and following Avago recommendations. * UL flammability level UL94 V-0. * Provides sufficient ESD creepage/clearance distance to avoid discharge up to 15 kV when assembled into a mouse according to usage instructions above. * For eye safety consideration, please refer to the technical report available on the web site, http://www.Avago.com * The 15.0 k resistor is determined by the absolute maximum rating of 50 mA for the HLMP-ED80XX000. The other resistor values for brighter bins will guarantee good signals with reduced power.
7
Alternative Application using Quadrature Output Pins
4.7 F 1.5 M 9 12 VDD CEXT
0.1 F 12 10
13 VDD GND GND
INTERNAL IMAGE SENSOR
HDNS-2100 LENS
HLMP-ED80
SURFACE 6 9
0.33 F VDD D+ D- GND SHLD 6 MHz 11 6 19 20 14 D+
CYPRESS CY7C63001A-PC
P0.1 2 P0.0 P0.2 P0.3 P1.1 XTALOUT P1.2 P0.5 P0.4 VSS VPP 7 8 P1.3 P1.0 1 3 4 16 15 5 2 3 4 5 15 1
XY_LED XA XB YB REFA YA PD SCLK REFB R_BIN OSC_IN
ADNS-2051
OSC_OUT 11 7
CERAMIC RESONATOR 18 MHz AVX KBR-18-00-MSA MURATA CSALS18M0X55-B0
13 D- 10 XTALIN
0.1 F 8 14
2.2 F
M R L
16 SDIO
R1
R1 VALUE (k) 15.0 15.0 15.0 15.0 15.0 15.0 ~ 18.0 15.0 ~ 22.0 15.0 ~ 27.0 15.0 ~ 33.0 15.0 ~ 37.0
LED BIN K L M N P Q R S T U
P0.6 17 P0.7 18
BUTTONS
PANASONIC EVQ SERIES ENCODER Z-WHEEL 1.5 k 7.5 k 3.3 V REGULATOR LP2950AC Z-3.3
D- RESISTOR CONNECTION ALTERNATIVE D- RESISTOR CONNECTION
Figure 9. Application using quadrature output pins
ADNS-2001 fig 09
Absolute Maximum Ratings
Parameter
Storage Temperature Operating Temperature Lead Solder Temperature Supply Voltage ESD Input Voltage Input Voltage VIN VIN -0.5 -0.5 VDD -0.5
Symbol
TS TA
Min.
-40 -15
Max.
85 55 260 5.5 2 VDD + 0.5 3.6
Units
C C C V kV V R_BIN V
Notes
For 10 seconds, 1.6 mm below seating plane. All pins, human body model MIL 883 Method 3015 PD, SDIO, SCLK, XA, XB, YA, YB, XY_LED, OSC_IN, OSC_OUT, REF_A
8
Recommended Operating Conditions
Parameter
Operating Temperature Power Supply Voltage
Symbol
TA VDD
Min.
0 4.25
Typ.
5.0
Max.
40 5.5
Units
C volts
Notes
Register values retained for voltage transients below 4.25 V but greater than 4 V. Peak to peak within 0-100 MHz. Set by ceramic resonator.
Power Supply Rise Time Supply Noise Clock Frequency Serial Port Clock Frequency Resonator Impendance Distance from Lens Reference Plane to Surface Speed Acceleration Light Level onto IC SDIO Read Hold Time SDIO Serial Write-Write Time SDIO Serial Write-Read Time SDIO Serial Read-Write Time SDIO Serial Read-Read Time
VRT VN fCLK SCLK XRES Z S A IRRINC tHOLD tSWW tSWR tSRW tSRR tCOMPUTE 80 100 100 100 100 120 120 3.2 2.3 0 2.4 17.4 18.0
100 100 18.7 fCLK/4 55 2.5 14 0.15 25,000 30,000
ms mV MHz MHz mm in/sec g mW/m2 s s s ns ns ms Results in 0.2 mm DOF. (See Figure 10.) @ frame rate = 1500/second. @ frame rate = 1500/second. = 639 nm = 875 nm Hold time for valid data. (Refer to Figure 28.) Time between two write commands. (Refer to Figure 31.) Time between write and read operation. (Refer to Figure 32.) Time between read and write operation. (Refer to Figure 33.) Time between two read commands. (Refer to Figure 33.) After tCOMPUTE, all registers contain data from first image after PD . Note that an additional 75 frames for AGC (shutter) stabilization may be required if mouse movement occurred while PD was high. (Refer to Figure 12.) Data valid time before the rising of SCLK. (Refer to Figure 26.) Pulse width to initiate the power down cycle @ 1500 fps. (Refer to Figure 12 and Figure 14.) Pulse width to reset the serial port @ 1500 fps (but may also initiate a power down cycle. Normal PD recovery sequence to be followed. (Refer to Figure 15.)
Data Delay after PD
SDIO Write Setup Time PD Pulse Width (to power down the chip) PD Pulse Width (to reset the serial port)
tSETUP tPDW
60 700
ns s
tPDR
100
s
Frame Rate Bin Resistor
FR R1 15 K
1500 15 K 37 K
frames/s See Frame_Period register section. Refer to Figure 8.
9
ADNS-2051
HDNS-2100
Z
OBJECT SURFACE
Figure 10. Distance from lens reference plane to surface
Fig 10 Distance from Lens Reference Plane to Surface
AC Electrical Specifications
Parameter Power Down
Electrical Characteristics over recommended operating conditions. Typical values at 25C, VDD = 5.0 V, 1500 fps, 18 MHz.
Symbol tPD Min. Typ. 700 Max. Units s Notes From PD Time uncertainty due to firmware delay. (Refer to Figure 12.)
Power Up from VDD
tPU
30
ms
From VDD to valid quad signals 705 sec + 40 frames
Rise and Fall Times:
SDIO
tr tf
30 16 50 20 40
ns ns ns ns ns
CL = 30 pF (the rise time is between 10% and 90%) CL = 30 pF (the fall time is between 10% and 90%) CL = 30 pF (the rise time is between 10% and 90%) CL = 30 pF (the fall time is between 10% and 90%) With HLMP-ED80-XX000 LED (the rise time is between 10% and 90%) With HLMP-ED80-XX000 LED (the fall time is between 10% and 90%) Serial port will reset if current transaction is not complete within tSPTT. (Refer to Figure 36.) Max. supply current during a VDD ramp from 0 to 5.0 V with > 500 s rise time. Does not include charging current for bypass capacitors.
XA, XB, YA, YB
tr tf
ILED
tr
tf
200
ns
Serial Port Transaction Timer
tSPTT
0.7
0.9
1.0
s
Transient Supply Current
IDDT
20
37
mA
10
Power Up from PD
tPUPD
50
ms
From PD to valid quad signals 705 sec + 75 frames. (Refer to Figure 12.)
DC Electrical Specifications
Parameter DC Supply Current (mouse moving) Peak Supply Current (mouse moving) DC Supply Current (mouse not moving) DC Supply Current (power down) SCLK, SDIO, PD Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage (XA, XB, YA, YB) Output High Voltage (XA, XB, YA, YB) Output Low Voltage (XY_LED) XY LED Current XY LED Current (fault mode) REF_A (normal mode) REF_A (power down mode)
Electrical Characteristics over recommended operating conditions. Typical values at 25C, VDD = 5.0 V, 18 MHz.
Symbol IDD AVG Min. Typ. 15 Max. 25 Units mA Notes No load on XA, XB, YA, YB, SCLK, SDIO. Excluding LED current. No load on XA, XB, YA, YB, SCLK, SDIO. Excluding LED current. No load on XA, XB, YA, YB, SCLK, SDIO. Excluding LED current. PD = high; SCLK, SDIO = GND or VDD; VDD = 4.25 V to 5.25 V.
IDD PEAK
20
mA
IDD
12
25
mA
IDDPD
170
240
A
VIL VIH VOL VOH VOL VOH VOL ILED ILED VREFA VREFA 3.3 3.3 Typ-15% 630/R1 0.6 * VDD 0.6 * VDD 0.5 * VDD
0.8 0.7 0.4
V V V V V V @ IOL = 2 mA (SDIO only) @ IOH = 2 mA (SDIO only) @ IOL = 0.5 mA. @ IOH = 0.5 mA . Refer to Figure 11. Refer to Figure 11, see table below. R1 < 200 . 1.5 K to 3.0 V or GND, PD = low. 1.5 K to 3.0 V or GND, PD = high.
1.1
V
Typ + 15% A 500 A V V
100
Typical LED Current Table
R1 Value k mA 15 42 18 35 22 29 27 23 33 19 37 17 LED current (typical)
NORMALIZED ILED - %
80 60 40 20 0
R = 15 k R = 30 k 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VOL (V)
Figure 11. Typical I-V characteristic of ADNS2051 XY_LED pin
ADNS-2051 fig 11
11
PD Pin Timing
PD
IDD tpd 75 FRAMES 705 s tpupd tCOMPUTE (SEE FIGURE 15)
Figure 12. PD timing normal mode
JOB 389 FIG 12 PD Timing Normal Mode
PD
I LED
PD
SCLK
tPDW 700 s
REGISTER READ OPERATION tCOMPUTE
(POWER DOWN)
Figure 13. PD timing sleep mode
JOB 389 FIG 13 PD Timing Sleep Mode
Figure 14. PD minimum pulse width
PD OSCILLATOR START 250 s LED CURRENT SCLK
JOB 389 FIG 14 PD MINIMUM PULSE WIDTH
RESET COUNT 455 s
INITIALIZATION 2410 s
NEW ACQUISITION
705 s
OPTIONAL SPI TRANSACTIONS WITH OLD IMAGE DATA tCOMPUTE
SPI TRANSACTIONS WITH NEW IMAGE DATA AT DEFAULT FRAME RATE
Figure 15. Detail of PD falling edge timing
Quadrature Mode Timing
JOB 389 FIG 15
The output waveforms emulate the output from encoders. With the resolution set to 400 cpi, from one to five quadrature states can exist within one frame time. The minimum state time is 133 s. If the resolution is 800 cpi, then up to ten quadrature states can exist within a frame time. If the motion within a frame is greater than these values, the extra motion will be reported in the
next frame. The following diagrams (see Figures 16, 17, and 18) show the timing for positive X motion, to the right or positive Y motion, up. If a power down via the PD pin occurs during a transfer, the transfer will resume after PD is de-asserted. The timing for that quadrature state will be increased by the length of the PD time.
12
X MOTION TO THE RIGHT Y MOTION UP XA/YA FIVE OR MORE XB/YB 133 s 133 s 133 s 133 s 133 s
XA/YA FOUR XB/YB 133 s 133 s 133 s 267 s
XA/YA THREE XB/YB 133 s 133 s 400 s
XA/YA TWO XB/YB 133 s 533 s
XA/YA ONE XB/YB 667 s
~ 667s @ 1500 FRAMES/SECOND ONE FRAME
Job 389 Fig 16 Quadrature States Per Frames (400 cpi Mode)
Figure 16. Quadrature states per frame (400 cpi mode)
13
X MOTION TO THE RIGHT Y MOTION UP
XA/YA TEN OR MORE XB/YB 66.7 s 66.7 s 66.7 s 66.7 s 66.7 s 66.7 s 66.7 s 66.7 s 66.7 s 66.7 s
XA/YA NINE XB/YB 66.7 s 66.7 s 66.7 s 66.7 s 66.7 s 66.7 s 66.7 s 66.7 s 133 s
XA/YA EIGHT XB/YB 66.7 s 66.7 s 66.7 s 66.7 s 66.7 s 66.7 s 66.7 s 200 s
XA/YA SEVEN XB/YB 66.7 s 66.7 s 66.7 s 66.7 s 66.7 s 66.7 s 266 s
XA/YA SIX XB/YB 66.7 s 66.7 s 66.7 s 66.7 s 66.7 s 333 s
~ 667s @ 1500 FRAMES/SECOND ONE FRAME
Figure 17. Quadrature states per frame (800 cp imode)
Job 389 Fig 17 Quadrature States Per Frames (800 cpi Mode)
14
X MOTION TO THE RIGHT Y MOTION UP XA/YA FIVE XB/YB 66.7 s 66.7 s 66.7 s 66.7 s 400 s
XA/YA FOUR XB/YB 66.7 s 66.7 s 66.7 s 476 s
XA/YA THREE XB/YB 66.7 s 66.7 s
XA/YA TWO XB/YB 66.7 s
XA/YA ONE XB/YB
~ 667s @ 1500 FRAMES/SECOND ONE FRAME Job 389 Fig 18 Quadrature States Per Frames (800 cpi Mode)
Figure 18. Quadrature states per frame (800 cpi mode)
15
Quadrature State Machine
The following state machine shows the states of the quadrature pins. The two things to note are that while the PD pin is asserted, the state machine is halted. Once PD is de-asserted, the state machine picks up from where it left off. State 0 is entered after a power up reset.
PD STATE 0
+1 -1
PD STATE 2 STATE X AND Y OUTPUT A 0 0 1 1 B 0 1 0 1
+1
-1
-1
+1
STATE 1 PD
-1 +1
0 1 2 3 PD
STATE 3
Figure 19. Quadrature state machine
Fig. 19 Quadrature State Machine
Quadrature Output Waveform
The two channel quadrature outputs are 5.0 volt CMOS outputs. The x count is used to generate the XA and XB signals, and y count is used for the YA and YB signals.
XA LEFT MOTION (-DIRECTION) XB -1 -1 -1 -1 MOTION COUNT
YA DOWN MOTION (- DIRECTION) YB -1 -1 -1 -1 MOTION COUNT
XA RIGHT MOTION (+ DIRECTION) XB +1 +1 +1 +1 MOTION COUNT
YA UP MOTION (+ DIRECTION) YB -1 -1 -1 -1 MOTION COUNT
Figure 20. Quadrature output waveform
Job 389 Fig 20 Quadrature Output Waveform
16
Typical Performance Characteristics
Performance characteristics over recommended operating conditions. Typical values at 25C, VDD = 5.0 V, 18 MHz.
Parameter Path Error (Deviation) Symbol PERROR Min. Typ. 0.5 Max. Units % Notes Path Error (Deviation) is the error from the ideal cursor path. It is expressed as a percentage of total travel and is measured over standard surfaces.
The following graphs (Figures 21, 22, 23, and 24) are the typical performance of the ADNS-2051 sensor, assembled as shown in the 2D assembly drawing with the HDNS-2100 Lens/Prism, the HDNS-2200 clip, and the HLMP-ED80-XX000 LED (page 3, Figure 4).
TYPICAL RESOLUTION vs. HEIGHT
500 450 400
COUNTS PER INCH
1.0 0.9
RELATIVE RESPONSIVITY
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 400 500 600 700 800 900 1000
350 300 250 200 150 100 50 0
Z
DOF DOF RECOMMENDED OPERATING REGION WHITE PAPER MANILA FOLDER BURL FORMICA DARK WALNUT BLACK COPY
-50 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 HEIGHT - mm (2.4 = NOMINAL FOCUS)
WAVELENGTH (nm)
Figure 21. Typical resolution vs. Z (comparative surfaces)[2,3]
ADNS-2051 fig 23
Figure 22. Wavelength responsitivity[1]
TYPICAL RESOLUTION vs. HEIGHT AT DIFFERENT LED CURRENT LEVELS [BRIGHTNESS] (MANILA FOLDER) 450 400
COUNTS PER INCH
Z DOF DOF
TYPICAL RESOLUTION vs. HEIGHT AT DIFFERENT LED CURRENT LEVELS [BRIGHTNESS] (BLACK COPY) 450 400 350 300 250 200 150 100 50 0
Z DOF DOF
350
COUNTS PER INCH
300 250 200 150 100 50
RECOMMENDED OPERATING REGION
100% 75% 50%
100% 75% 50%
RECOMMENDED OPERATING REGION
0 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 HEIGHT - mm (2.4 = NOMINAL FOCUS)
-50 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 HEIGHT - mm (2.4 = NOMINAL FOCUS)
Figure 23. Typical resolution vs. z (manila folder and LED variation)[2,3]
ADNS-2051 fig 21
Figure 24. Typical resolution vs. z (black copy and LED variation)[2,3]
ADNS-2051 fig 24
Note: 1. The ADNS-2051 is designed for optimal performance when used with the HLMP-ED80-XX000 (red LED 639 nm). For use with other LED colors (i.e., blue, green), please consult factory. When using alternate LEDs, there may also be performance degradation and additional eye safety considerations. 2. Z = Distance from Lens Reference plane to Surface. 3. DOF = Depth of Field.
17
Synchronous Serial Port
The synchronous serial port is used to set and read parameters in the ADNS-2051, and can be used to read out the motion information instead of the quadrature data pins. The port is a two wire, half duplex port. The host microcontroller always initiates communication; the ADNS-2051 never initiates data transfers. SCLK: SDIO: PD: The serial port clock. It is always generated by the master (the micro-controller). The data line. A third line is sometimes involved. PD (Power Down) is usually used to place the ADNS-2051 in a low power mode to meet USB suspend specification. PD can also be used to force resynchronization between the micro-controller and the ADNS-2051 in case of an error.
Write Operation
Write operations, where data is going from the microcontroller to the ADNS-2051, is always initiated by the micro-controller and consists of two bytes. The first byte contains the address (seven bits) and has a "1" as its MSB to indicate data direction. The second byte contains the data. The transfer is synchronized by SCLK. The micro-controller changes SDIO on falling edges of SCLK. The ADNS-2051 reads SDIO on rising edges of SCLK.
SCLK CYCLE # SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SDIO
1
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
DON'T CARE
SDIO DRIVEN BY MICRO-CONTROLLER
Figure 25. Write operation
ADNS-2051 fig 25
120 ns 120 ns SCLK
SDIO 120 ns, MIN. tsetup = 60 ns, MIN.
Figure 26. SDIO setup and hold times SCLK pulse width
ADNS-2051 fig 26
18
Read Operation
A read operation, which means that data is going from the ADNS-2051 to the micro-controller, is always initiated by the micro-controller and consists of two bytes. The first byte contains the address, is written by the micro-controller, and has a "0" as its MSB to indicate data direction. The second byte contains the data and is driven by the ADNS-2051. The transfer is synchronized by SCLK. SDIO is changed on falling edges of SCLK and read on every rising
SCLK CYCLE # SCLK SDIO 0 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8
edge of SCLK. The micro-controller must go to a high Z state after the last address data bit. The ADNS-2051 will go to the high Z state after the last data bit (see detail "B" in Figure 28). One other thing to note during a read operation is that SCLK will need to be delayed after the last address data bit to ensure that the ADNS-2051 has at least 100 s to prepare the requested data. This is shown in the timing diagrams below.
9 10 11 12 13 14 15 16
SDIO DRIVEN BY MICRO-CONTROLLER DETAIL "A"
SDIO DRIVEN BY ADNS-2051 DETAIL "B"
Figure 27. Read operation
DETAIL "A" tHOLD 100 s, MIN. SCLK MICROCONTROLLER TO ADNS-2051 SDIO HANDOFF SDIO A1 60 ns, MIN. A0 120 ns, MIN. 120 ns, MAX.
ADNS-2051 fig 27
0 ns, MIN. Hi-Z D7 0 ns, MIN. 120 ns, MAX. D6
Figure 28. Microcontroller to ADNS-2051 SDIO handoff
DETAIL "B" 120 ns, MIN. SCLK ADNS-2051 TO MICROCONTROLLER SDIO HANDOFF SDIO D0 RELEASED BY 2051
ADNS-2051 fig 28 10 ns, MAX.
Note: The 120 ns high state of SCLK is the minimum data hold time of the ADNS-2051. Since the falling edge of SCLK is actually the start of the next read or write command, the ADNS2051 will hold the state of D0 on the SDIO line until the falling edge of SCLK. In both write and read operations, SCLK is driven by the micro-controller. Serial port communications is not allowed while PD (power down) is high. See "Error Detection and Recovery" regarding resynchronizing via PD.
R/W BIT OF NEXT ADDRESS
DRIVEN BY MICRO
Figure 29. ADNS-2051 to microcontroller SDIO handoff
ADNS-2051 fig 29
19
Forcing the SDIO Line to the Hi-Z State
There are times when the SDIO line from the ADNS2051 should be in the Hi-Z state. If the microprocessor has completed a write to the ADNS-2051, the SDIO line is Hi-Z, since the SDIO pin is still configured as an input. However, if the last operation from the microprocessor was a read, the ADNS-2051 will hold the D0 state on SDIO until a falling edge of SCLK.
100 s PD
To place the SDIO pin into the Hi-Z state, raise the PD pin for 100 s (min). The PD pin can stay high, with the ADNS-2051 in the shutdown state, or the PD pin can be lowered, returning the ADNS-2051 to normal operation. The SDIO line will now be in the Hi-Z state.
SDIO
Hi-Z
Figure 30. SDIO Hi-Z state and timing
Required ADNS-2051 fig 30 Read and Write Commands (tsxx) Timing between
There are minimum timing requirements between read and write commands on the serial port. If the rising edge of the SCLK for the last data bit of the second write command occurs before the 100 microsecond required delay, then the first write command may not complete correctly.
tSWW >100 s
SCLK ADDRESS DATA ADDRESS DATA
WRITE OPERATION
WRITE OPERATION
Figure 31. Timing between two write commands
If the rising edge of SCLK for the last address bit of the read command occurs before the 100 microsecond required delay, then the write command may not complete correctly.
tSWR >100 s
ADNS-2051 fig 31
***
SCLK ADDRESS DATA ADDRESS
***
WRITE OPERATION
NEXT READ OPERATION
Figure 32. Timing between write and read commands
ADNS-2051 fig 32
20
The falling edge of SCLK for the first address bit of either the read or write command must be at least 120 ns after the last SCLK rising edge of the last data bit of the previous read operation.
tHOLD >100 s tSRW, tSRR >120 s
***
SCLK ADDRESS READ OPERATION DATA ADDRESS
***
NEXT READ OR WRITE OPERATION
Figure 33. Timing between read and either write or subsequent read commands
ADNS-2051 fig 33
SCLK DATA PD >1 s
Figure 34. Timing between SCLK and PD rising edge
ADNS-2051 fig 34
21
Error Detection and Recovery
1. The ADNS-2051 and the micro-controller might get out of synchronization due to ESD events, power supply droops or micro-controller firmware flaws. In such a case, the micro-controller should raise PD for 100 s. The ADNS-2051 will reset the serial port but will not reset the registers and be prepared for the beginning of a new transmission. 2. The ADNS-2051 has a transaction timer for the serial port. If the sixteenth SCLK rising edge is spaced more than approximately 0.9 seconds from the first SCLK edge of the current transaction, the serial port will reset. 3. Invalid addresses: - Writing to an invalid address will have no effect. Reading from an invalid address will return all zeros. 4. Collision detection on SDIO - The only time that the ADNS-2051 drives the SDIO line is during a READ operation. To avoid data collisions, the micro-controller should relinquish SDIO before the falling edge of SCLK after the last address bit. The ADNS-2051 begins to drive SDIO after the next rising edge of SCLK. The ADNS-2051 relinquishes SDIO within 120 ns of the falling SCLK edge after the last data bit. The microcontroller can begin driving SDIO any time afterthat. In order to maintain low power consumption in nor mal operation or when the PD pin is pulled high, the micro-controller should not leave SDIO floating un til the next transmission (although that will not cause any communication difficulties).
VDD PD
5. In case of synchronization failure, both the ADNS-2051 and the micro-controller may drive SDIO. The ADNS2051 can withstand 30 mA of short circuit current and will withstand infinite duration short circuit conditions. 6. Termination of a transmission by the micro-controller may sometimes be required (for example, due to a USB suspend interrupt during a read operation). To accomplish this the micro-controller should raise PD. The ADNS-2051 will not write to any register and will reset the serial port (but nothing else) and be prepared for the beginning of future transmissions after PD goes low. 7. The micro-controller can verify success of write operations by issuing a read command to the same address and comparing written data to read data. 8. The micro-controller can verify the synchronization of the serial port by periodically reading the product ID register.
SCLK ADDRESS = 0x00 SDIO DATA = 0x02
PROBLEM AREA
Figure 35. Power up serial port watchdog timer sequence
ADNS-2051 fig 35
22
Notes on Power up and the Serial Port
The sequence in which VDD, PD, SCLK, and SDIO are set during powerup can affect the operation of the serial port. The diagram below shows what can happen shortly after powerup when the microprocessor tries to read data from the serial port. This diagram shows the VDD rising to valid levels, at some point the microcontroller starts its program, sets the SCLK and SDIO lines to be outputs, and sets them high. It then waits to ensure that the ADNS-2051 has powered up and is ready to communicate. The microprocessor then tries to read from location 0x00, Product_ID, and is expecting a value of 0x02. If it receives this value, it then knows that the communication to the ADNS-2051 is operational. The problem occurs if the ADNS-2051 powers up before the microprocessor sets the SCLK and SDIO lines to be
VDD > tSPTT PD
outputs and high. The ADNS-2051 sees the raising of the SCLK as a valid rising edge, and clocks in the state of the SDIO as the first bit of the address (sets either a read or a write depending upon the state). In the case of SDIO low, then a read operation has started. When the microprocessor begins to actually send the address, the ADNS-2051 already has the first bit of an address. When the seventh bit is sent by the micro, the ADNS-2051 has a valid address, and drives the SDIO line high within 120 ns (see detail "A" in Figure 27 and Figure 28). This results in a bus fight for SDIO. Since the address is wrong, the data sent back will be incorrect. In the case of SDIO high, a write operation is started. The address and data are out of synchronization, and the wrong data will be written to the wrong address.
SCLK ADDRESS = 0x00 SDIO DATA = 0x02
Figure 36. Power up serial port watchdog timer sequence
4 ms
ADNS-2051 fig 36
VDD PD
SCLK ADDRESS = 0x00 SDIO DATA = 0x02
Figure 37. Power up serial port PD sync sequence
Two Solutions
ADNS-2051 fig 37
2. PD Sync The PD line can be used to resync the serial port. If the microprocessor waits for 4 ms from VDD valid, and then outputs a valid PD pulse (see Figure 15), then the serial port will be ready for data.
There are two different ways to solve the problem, waiting for the serial port watchdog timer to time out, or using the PD line to reset the serial port. 1. Serial Port Watchdog Timer Timeout If the microprocessor waits at least tSPTT from VDD valid, it will ensure that the ADNS-2051 has powered up and the watchdog timer has timed out. This assumes that the microprocessor and the ADNS-2051 share the same power supply. If not, then the microprocessor must wait tSPTT from ADNS-2051 VDD valid. Then when the SCLK toggles for the address, the ADNS-2051 will be in sync with the microprocessor. 23
Resync Note
If the microprocessor and the ADNS-2051 get out of sync, then the data either written or read from the registers will be incorrect. An easy way to solve this is to output a PD pulse to resync the parts after an incorrect read.
SPI communication code for the Cypress CY7C63000 or CY7C63001
(Please consult factory for the CY7C63722 or CY7C63723 codes.)
Note: This programming sequence is not covered in Avago's product warranty. It is only a recommended example when using the mentioned Cypress microcontrollers. For the latest updates on Cypress microcontrollers, please contact Cypress at email: usbapps@cypress.com or call (858) 613-7929 (US).
The following code can be used to implement the SPI data communications. See the schematic in Figure 9.
; Notes: ; CY7C6300120pinpackage ; ADNS-2051 ; SDIOlineconnectedtopin5(P1.0) ; PDconnectedtopin16(P1.1) ; SCLKlineconnectedtopin15(P1.3) ; I/Oport Port1_Data: equ 01h ; GPIOdataport1 Port1_Interrupt: equ 05h ; Interruptenableforport1 Port1_Pullup: equ 09h ; Pullupresistorcontrolforport1 ; ; Portbitdefinitions SDIO: equ 01h ; bit0 PD: equ 02h ; bit1 SCLK: equ 08h ; bit3 Pt1_Current: equ 00h ; port1currentsetting ; ; GPIOIsinkregisters Port1_Isink: equ 38h Port1_Isink0: equ 38h Port1_Isink1: equ 39h Port1_Isink3: equ 3Bh ; ; ; datamemoryvariables spi_addr: equ 40h ; addressofspiwrites spi_data: equ 41h ; dataofspiwrites bit_counter: equ 44h ; SPIbitcounter port1_wrote: equ 45h ; whatwewrotelast ; ; ; initializePort1 ; movA,Pt1_Current ; selectDACsetting iowrPort1_Isink0 ; isinkcurrentPort1bit[0] iowrPort1_Isink1 ; isinkcurrentPort1bit[1] iowrPort1_Isink3 ; isinkcurrentPort1bit[3] movA,0h ; enablePort1bit[7:0]pullups iowrPort1_Pullup movA,~(PD|SDIO) ; turnontheADNS-2051 mov[port1_wrote],A movA,[port1_wrote] iowrPort1_Data ; PDlow,SCLK,SDIO movA,0 iowrPort1_Interrupt ; disableport1interrupts ; TherearepossibleproblemswiththeSPIportifthemicrocontrollerstartsexecuting ; instructionsbeforetheADNS-2051sensorhaspoweredup.Seepage18fordetails. ; ItisassumedthatpowertothemicrocontrollerisOKifthenextinstructionscanbeexecuted. ; TheseinstructionswillresettheSPIportofthesensor.
24
Resync_sensor: movA,~(SCLK|SDIO|PD) ; settheSCLK,SDIOandPDlineslow and[port1_wrote],A movA,[port1_wrote] iowrPort1_Data ; Ifthepowertothesensorneedsmoretime ; tostabilize,insertadelayhere calldelay700us ; waitabout4millisecondsforthesensor calldelay700us ; oscillatortostabilize calldelay700us calldelay700us calldelay700us calldelay700us movA,(SCLK|SDIO|PD ; settheSCLK,SDIOandPDlineshigh or[port1_wrote],A ; thisshutsdowntheoscillatorand movA,[port1_wrote] ; resetstheSPIport iowrPort1_Data calldelay700us ; waitforthePDtoresetthepart movA,~PD ; setthePDlinelowtoputthesensor and[port1_wrote],A ; backintonormaloperation movA,[port1_wrote] iowrPort1_Data calldelay700us ; waitabout4millisecondsforthesensor calldelay700us ; oscillatortostabilize calldelay700us calldelay700us calldelay700us calldelay700us ; sensorSPIportnowinsync ; ; ReadSPIroutine ; ; IncludesdelaysforlongtracesorcablesbetweentheuPandADNS-2051 ; HascorrecttimingofSCLKandSDIO ; ; Onentry: spi_addr=AddressofSPIregisterintheADNS-2051 ; spi_data=undefined ; ; Onexit spi_addr=undefined ; spi_data=registercontentsfromADNS-2051 ; ReadSPI: movA,64 ; wait200us(optional) mov[bit_counter],A ; (about3usperloop) Waitrspi: nop nop nop nop nop nop dec[bit_counter] jnzWaitrspi ; readaddress movA,~80h and[spi_addr],A ; lowerMSBofaddress(read) callwriteaddr ; wait200us(about3usperloop)(100usminimumrequired) movA,64 ; waitfordatatobeready mov[bit_counter],A Waitrspi2: nop nop nop nop nop nop dec[bit_counter] jnzWaitrspi2 movA,0h ; clearthedata
25
mov[spi_data],A movA,08h mov[bit_counter],A movA,SDIO or[port1_wrote],A movA,[port1_wrote] ; writea1toSDIO iowrPort1_Data nextr: movA,~SCLK ; lowerSCLK and[port1_wrote],A movA,[port1_wrote] iowrPort1_Data nop ; waitforcabletosettle nop ; ifADNS-2051isconnectedto nop ; ICviashortPCBtraces, nop ; thenthenumberofNOPscan nop ; reducedoreliminated nop nop movA,[spi_data] ; shiftnextbit asl mov[spi_data],A ; shiftnextbit iordPort1_Data ; readSDIO andA,SDIO jzrdx rd1: movA,01h or[spi_data],A rdx: movA,SCLK ; raiseSCLK or[port1_wrote],A movA,[port1_wrote] iowrPort1_Data nop ; waitforcabletosettle nop nop nop nop nop nop dec[bit_counter] jnznextr ret ; ; WriteSPIroutine ; ; IncludesdelaysforlongtracesorcablesbetweentheuPandADNS-2051. ; HascorrecttimingofSCLKandSDIO ; ; Onentry: spi_addr=AddressofSPIregisterintheADNS-2051 ; spi_data=DatatobewrittentotheSPIregister ; ; Onexit spi_addr=undefined ; spi_data=undefined ; WriteSPI: movA,64 ; wait200us(optional) mov[bit_counter],A ; about3usperloop Waitspi: nop nop nop nop nop nop dec[bit_counter] jnzWaitspi ; writeaddress
26
writeaddr: nexta: addr1: addr0: addrx: wrdata: nextw: wr1: wr0: wrx:
movA,80h or[spi_addr],A callwriteaddr jmpwrdata movA,08h mov[bit_counter],A movA,~SCLK and[port1_wrote],A movA,[port1_wrote] iowrPort1_Data movA,[spi_addr] asl mov[spi_addr],A jncaddr0 movA,SDIO or[port1_wrote],A jmpaddrx movA,~SDIO and[port1_wrote],A movA,[port1_wrote] iowrPort1_Data nop nop nop nop nop nop nop movA,SCLK or[port1_wrote],A movA,[port1_wrote] iowrPort1_Data nop nop nop nop nop nop nop dec[bit_counter] jnznexta ret movA,08h mov[bit_counter],A movA,~SCLK and[port1_wrote],A movA,[port1_wrote] iowrPort1_Data movA,[spi_data] asl mov[spi_data],A jncwr0 movA,SDIO or[port1_wrote],A jmpwrx movA,~SDIO and[port1_wrote],A movA,[port1_wrote] iowrPort1_Data nop nop nop nop nop nop nop
; setMSBofaddress(write) ; 8bitstoshiftout ; lowerSCLK
; shiftnextbit
; raiseSDIO ; lowerSDIO ; waitforcabletosettle
; raiseSCLK ; ADNS-2051readstheaddressbit ; waitforcabletosettle
; 8bitsofdata ; lowerSCLK
; shiftnextbit
; raiseSDIO ; lowerSDIO ; waitforcabletosettle
27
delay700us: waitd0: ; ; ; ; ; ; ; ;
movA,SCLK or[port1_wrote],A movA,[port1_wrote] iowrPort1_Data nop nop nop nop nop nop nop dec[bit_counter] jnznextw ret movA,ffh mov[bit_counter],A nop nop nop nop nop nop dec[bit_counter] jnzwaitd0 ret
;raiseSCLK ; ADNS-2051readsthedatabit ; waitforcabletosettle
; waitfor710us ; reusebit_counter
; 2us
Examplecallingsyntax
WriteSPI Setregister0ato40h,LEDblinkmode movA,0ah mov[spi_addr],A movA,40h mov[spi_data],A callWriteSPI ReadSPI Readregister02h,themotionregister movA,02h mov[spi_addr],A callReadSPI ; ; ; ; moveaddressintoA moveaddressintospi_addr callReadSPI,onreturn,dataisinspi_data, spi_addrisundefined ; moveaddressintoA ;moveaddressintospi_addr ; movedataintoA ; movedataintospi_data ; callWriteSPIroutine,onreturn, ; spi_addrandspi_datawillbeundefined
28
Registers
The ADNS-2051 can be programmed through registers, via the serial port, and configuration and motion data can be read from these registers.
Address 0x00 0x01 0x02 0x03 0x04 0x05 Register Product_ID Revision_ID Motion Delta_X Delta_Y SQUAL Address 0x06 0x07 0x08 0x09 0x0a 0x0b Register Average_Pixel Maximum_Pixel Reserved Reserved Configuration_bits Reserved Address 0x0c 0x0d 0x0e 0x0f 0x10 0x11 Register Data_Out_Lower Data_Out_Upper Shutter_Lower Shutter_Upper Frame_Period_Lower Frame_Period_Upper
Product_ID Access: Read
Bit Field 7 PID7 6 PID6 5 PID5
Address: 0x00 Reset Value: 0x02
4 PID4 3 PID3 2 PID2 1 PID1 0 PID0
Data Type: Eight bit number with the product identifier. USAGE: The value in this register does not change, it can be used to verify that the serial communications link is OK.
Revision_ID Access: Read
Bit Field 7 RID7 6 RID6 5 RID5
Address: 0x01 Reset Value: 0xNN
4 RID4 3 RID3 2 RID2 1 RID1 0 RID0
Data Type: Eight bit number with current revision of the IC. USAGE: NN is a value between 00 and FF which represent the current design revision of the device.
Motion Access: Read
Bit Field Data Type: Bit field 7 MOT 6 Reserved
Address: 0x02 Reset Value: 0x00
5 FAULT 4 OVFY 3 OVFX 2 Reserved 1 Reserved 0 RES
USAGE: Register 0x02 allows the user to determine if motion has occurred since the last time it was read. If so, then the user should read registers 0x03 and 0x04 to get the accumulated motion. It also tells if the motion buffers have overflowed and whether or not an LED fault occurred since the last reading. The current resolution is also shown.
29
Field Name MOT
Description Motion since last report or PD 0 = No motion 1 = Motion occurred, data ready for reading in Delta_X and Delta_Y registers Reserved for future LED Fault detected - set when R_BIN is too low or too high, shorts to VDD or Ground 0 = No fault 1 = Fault detected Motion overflow Y, Y buffer has overflowed since last report 0 = No overflow 1 = Overflow has occurred Motion overflow X, X buffer has overflowed since last report 0 = No overflow 1 = Overflow has occurred Reserved for future Reserved for future Resolution in counts per inch 0 = 400 1 = 800
Reserved FAULT
OVFY
OVFX
Reserved Reserved RES
Notes for Motion: 1. Reading this register freezes the Delta_X and Delta_Y register values. Read this register before reading the Delta_X and Delta_Y registers. If Delta_X and Delta_Y are not read before the motion register is read a second time, the data in Delta_X and Delta_Y will be lost. 2. Avago RECOMMENDS that registers 0x02, 0x03 and 0x04 be read sequentially. 3. Internal buffers can accumulate more than eight bits of motion for X or Y. If either one of the internal buffers overflows, then absolute path data is lost, and the OVFX or OVFY bit is set. These bits (OVFX and OVFY) are cleared once some motion has been read from the Delta_X and Delta_Y registers, and if the buffers are not at full scale. Since more data is present in the buffers, the cycle of reading the Motion, Delta_X and Delta_Y registers should be repeated until the motion bit (MOT) is cleared. Until MOT is cleared, either the Delta_X or Delta_Y registers will read either positive or negative full scale. If the motion register has not been read for a long time, at 400 cpi it may take up to 16 read cycles to clear the buffers, at 800 cpi, up to 32 cycles. 4. FAULT is a sticky bit that is cleared by reading the Motion register. It signifies that an LED fault has occurred since the last time the motion register was read. Once an LED fault has cleared, the hardware will drive the LED normally.
Delta_X Access: Read
Bit Field 7 X7 6 X6 5 X5
Address: 0x03 Reset Value: 0x00
4 X4 3 X3 2 X2 1 X1 0 X0
Data Type: Eight bit 2`s complement number. USAGE: X movement is counts since last report. Absolute value is determined by resolution. Reading clears the register.
MOTION
-128
-127
-2
-1
0
+1
+2
+126
+127
DELTA_X
80
81
FE
FF
00
01
02
7E
7F
ADNS-2051 Delta X
30
Delta_Y Access: Read
Bit Field 7 Y7 6 Y6 5 Y5
Address: 0x04 Reset Value: 0x00
4 Y4 3 Y3 2 Y2 1 Y1 0 Y0
Data Type: Eight bit 2`s complement number. USAGE: Y movement is counts since last report. Absolute value is determined by resolution. Reading clears the register.
MOTION
-128
-127
-2
-1
0
+1
+2
+126
+127
DELTA_Y
80
81
FE
FF
00
01
02
7E
7F
Surface_Quality Access: Read
Bit Field 7 SQ7 6 SQ6 5 SQ5
4
Address: 0x05 Reset Value: 0x00 ADNS-2051 Delta Y
3 2 SQ3 SQ2
1 SQ1
0 SQ0
SQ4
Data Type: Eight bit number. USAGE: SQUAL is a measure of the number of features visible by the sensor in the current frame. The maximum value is 255. Since small changes in the current frame can result in changes in SQUAL, variations in SQUAL when looking at a surface are expected. The graph below shows 250 sequentially acquired SQUAL values, while a sensor was moved slowly over white paper. SQUAL is nearly equal to zero, if there is no surface below the sensor.
SQUAL VALUES (WHITE PAPER) 256
SQUAL VALUE
192 128 64 0
0
25
50
75
100
125
150
175
200
225
250
NORMALIZED SQUAL COUNTS
The focus point is important and could affect the squal value, the graph below ADNS-2051 clearly shows that the showing another setup with various z-height. The graph Squal Values squal count is dependent on focus distance. Note: This graph is obtained by getting multiple readings over different heights.
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0
-1.0 -0.8 -0.5 -0.3
X+ 3 X X - 3
0 0.25 0.5 0.75 1.0
DELTA FROM NOMINAL FOCUS (mm)
Figure 38. Typical mean squal vs. Z (white paper)
ADNS-2051 fig 38
31
Average_Pixel Access: Read
Bit Field 7 0 6 0 5 AP5
Address: 0x06 Reset Value: 0x00
4 AP4 3 AP3 2 AP2 1 AP1 0 AP0
Data Type: Six bit number. USAGE: Average Pixel value in current frame. Minimum value = 0, maximum = 63. The average pixel value can be adjusted every frame. Shown below is a graph of 250 sequentially acquired average pixel values, while the sensor was moved slowly over white paper.
AVERAGE PIXEL (WHITE PAPER)
AVERAGE PIXEL VALUE
64 48 32 16 0
0
25
50
75
100
125
150
175
200
225
250
Maximum_Pixel Access: Read
Bit Field 7 0 6 0 5 MP5
Address: 0x07 Average Pixel ADNS-2051 Reset Value: 0x00
4 MP4 3 MP3 2 MP2 1 MP1 0 MP0
Data Type: Six bit number. USAGE: Maximum Pixel value in current frame. Minimum value = 0, maximum value = 63. The maximum pixel value can be adjusted every frame. Shown below is a graph of 250 sequentially acquired maximum pixel values, while the sensor was moved slowly over white paper.
MAXIMUM PIXEL (WHITE PAPER)
MAXIMUM PIXEL VALUE
64 48 32 16 0
0
25
50
75
100
125
150
175
200
225
250
Reserved Reserved
Address: 0x08 Address: 0x09
ADNS-2051 Max. Pixel
32
Configuration_bits Access: Read/Write
Bit Field Data Type: Bit field 7 RESET 6 LED_MODE
Address: 0x0a Reset Value: 0x00
5 Sys Test 4 RES 3 PixDump 2 Reserved 1 Reserved 0 Sleep
USAGE: Register 0x0a allows the user to change the configuration of the sensor. Shown below are the bits, their default values, and optional values.
Field Name RESET
Description Power up defaults (bit always reads 0) 0 = No effect 1 = Reset registers and bits to power up default settings (bold entries) LED Shutter Mode 0 = Shutter mode off (LED always on) (even if no motion up to 1 sec.) 1 = Shutter mode on (LED only on when the electronic shutter is open) System Tests (bit always reads 0) 0 = No tests 1 = perform all system tests, output 16 bit CRC via Data_Out_Upper and Data_Out_Lower registers. Note: Since part of the system test is a RAM test, the RAM will be overwritten with the default values when the test is done. If any configuration changes from the default are needed for operation, make the changes AFTER the system test is run. This operation requires substantially more time to complete than other register transactions.
LED_MODE
Sys Test
RES
Resolution in counts per inch 0 = 400 1 = 800 Dump the pixel array through Data_Out_Upper and Data_Out_Lower, 256 bytes 0 = disabled 1 = dump pixel array Reserved Reserved Sleep Mode 0 = Normal, fall asleep after one second of no movement (1500 frames/s) 1 = Always awake
Pix Dump
Reserved Reserved Sleep
Reserved
Address: 0x0b
33
Data_Out_Lower Access: Read
Bit Field 7 DO7 6 DO6 5 DO5
Address: 0x0c Reset Value: undefined
4 DO4 3 DO3 2 DO2 1 DO1 0 DO0
Data_Out_Upper Access: Read
Bit Field 7 DO15 6 DO14 5 DO13
Address: 0x0d Reset Value: undefined
4 DO12 3 DO11 2 DO10 1 DO9 0 DO8
Data Type: Sixteen bit word. USAGE: Data can be written to these registers from the system self test, or the pixel dump command. The data can be read out 0x0d, or 0x0d first, then 0x0c.
Data_Out_Upper System test result 1: System test result 2: Pixel Dump command FE 4D Pixel Address
Data_Out_Lower D4 10 Pixel Data (Lower 6 bits)
Note One of two results returned. These values are subject to change with each device design revision.
Once the pixel dump command is given, the sensor writes the address and the value for the first pixel into the Data_Out_Upper and Data_Out_Lower registers. The MSB of Data_Out_Lower is the status bit for the data. If the bit is high, the data are NOT valid. Once the MSB is low, the data for that particular read are valid and should be saved. The pixel address and data will then be incremented on the next frame. Once the pixel dump is complete, the PixDump bit in register 0x0a should be set to zero. To obtain an accurate image, the LED needs to be turned on by changing the sleep mode of the configuration register 0x0a to always awake.
34
Pixel Address Map
(Looking through the HDNS-2100 Lens)
LAST PIXEL FF EF DF CF BF AF 9F 8F 7F 6F 5F 4F 3F 2F 1F 0F FE EE DE CE BE AE 9E 8E 7E 6E 5E 4E 3E 2E 1E 0E FD ED DD CD BD AD 9D 8D 7D 6D 5D 4D 3D 2D 1D 0D FC EC DC CC BC AC 9C 8C 7C 6C 5C 4C 3C 2C 1C 0C FB EB DB CB BB AB 9B 8B 7B 6B 5B 4B 3B 2B 1B 0B FA EA DA CA BA AA 9A 8A 7A 6A 5A 4A 3A 2A 1A 0A F9 E9 D9 C9 B9 A9 99 89 79 69 59 49 39 29 19 09 F8 E8 D8 C8 B8 A8 98 88 78 68 58 48 38 28 18 08 F7 E7 D7 C7 B7 A7 97 87 77 67 57 47 37 27 17 07 F6 E6 D6 C6 B6 A6 96 86 76 66 56 46 36 26 16 06 F5 E5 D5 C5 B5 A5 95 85 75 65 55 45 35 25 15 05 F4 E4 D4 C4 B4 A4 94 84 74 64 54 44 34 24 14 04 F3 E3 D3 C3 B3 A3 93 83 73 63 53 43 33 23 13 03 F2 E2 D2 C2 B2 A2 92 82 72 62 52 42 32 22 12 02 F1 E1 D1 C1 B1 A1 91 81 71 61 51 41 31 21 11 01 F0 E0 D0 C0 B0 A0 90 80 70 60 50 40 30 20 10 00 FIRST PIXEL
TOP X-RAY VIEW OF MOUSE
ADNS-2001 Pixel Address Map
LB RB
POSITIVE Y
1
A2051 YYWW
16
8
9
POSITIVE X
Figure 39. Directions are for a complete mouse, with the HDNS-2100 lens
ADNS-2051 fig 39
35
Pixel Dump Pictures
The following images (Figure 40) are the output of the pixel dump command. The data ranges from zero for complete black, to 63 for complete white. An internal AGC circuit adjusts the shutter value to keep the brightest feature (max. pixel) in the mid 50s.
(a) White Paper
(b) Manila Folder
(c) Neoprene Mouse Pad (Gray)
(d) USAF Test Chart Group 3, Element 1 8 line pairs per mm
Figure 40. Pixel dump pictures
36
Shutter_Lower Access: Read
Bit Field 7 S7 6 S6 5 S5
Address: 0x0e Reset Value: 0x64
4 S4 3 S3 2 S2 1 S1 0 S0
Shutter_Upper Access: Read
Bit Field 7 S15 6 S14 5 S13
Address: 0x0f Reset Value: 0x00
4 S12 3 S11 2 S10 1 S9 0 S8
Data Type: Sixteen bit word. USAGE: Units are clock cycles; default value is 64. Read Shutter_Upper first, then Shutter_Lower. They should be read consecutively. The shutter is adjusted to keep the average and maximum pixel values within normal operating ranges. The shutter value can be adjusted to a new value on every frame. When the shutter adjusts, it changes by 1/16 of the current value. Shown below is a graph of 250 sequentially acquired shutter values, while the sensor was moved slowly over white paper.
SHUTTER VALUES (WHITE PAPER) 800
SHUTTER VALUE (CLOCK CYCLES)
600 400 200 0
0
25
50
75
100
125
150
175
200
225
250
The focus point is important and could affect the shutter value. The graph below shows another setup with various z-height. This graph clearly shows that the shutter value ADNS-2051 Shutter Value is dependent on focus distance.
NORMALIZED SHUTTER VALUE (COUNTS) TYPICAL SHUTTER vs. Z (WHITE PAPER) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0
-1.0 -0.8 -0.5 -0.3 0 0.25 0.5 0.75 1.0
X+ 3 X X - 3
DISTANCE FROM NOMINAL FOCUS (mm)
Figure 41. Typical shutter vs. Z (white paper)
ADNS-2051 Shutter Graph
Note: This graph shows average readings over different heights. 37
The maximum value of the shutter is dependent upon the frame rate and clock frequency. The formula for the maximum shutter value is: Clock Frequency Max. Shutter Value = Frame Rate -2816 For a clock frequency of 18 MHz, the following table shows the maximum shutter value. 1 clock cycle is 55.56 nsec.
Max Shutter Frames/second 2300 2000 1500 1000 500 Decimal 5010 6184 9184 15184 33184 Hex 0x1392 0x1828 0x23E0 0x3B50 0x81A0 Shutter Upper 13 18 23 3B 81 Lower 92 28 E0 50 A0
Default Max. Shutter
Frame_Period_Lower Access: Read/Write
Bit Field 7 FP7 6 FP6 5 FP5
Address: 0x10 Reset Value: 0x20
4 FP4 3 FP3 2 FP2 1 FP1 0 FP0
Frame_Period_Upper Access: Read/Write
Bit Field 7 FP15 6 FP14 5 FP13
Address: 0x11 Reset Value: 0xd1
4 FP12 3 FP11 2 FP10 1 FP9 0 FP8
Data Type: Sixteen bit 2`s complement word. USAGE: The frame period counter counts up until it overflows. Units are clock cycles. The formula is:
Clock Rate = Counts (decimal) Frame Rate
Counts (hex)
Counts (2`s complement hex)
For an 18 MHz clock, here are the Frame_Period values for popular frame rates. Counts Frames/second 2300* 2000* 1500 1000 500 Decimal 7826 9000 12000 18000 36000 Hex 0x1E92 0x2328 0x2EE0 0x4650 0x8CA0 2`s Comp 0xE16E 0xDCD8 0xD120 0xB9B0 0x7360 Frame_Period Upper E1 DC D1 B9 73 Lower 6E D8 20 B0 60
Default Frame Time Minimum Frame Time
*Note: To optimize tracking performance on dark surfaces, it is recommended that an adaptive frame rate based on shutter value be implemented, for frame rates greater than 1500. Changing the frame rate results in changes in the maximum speed, acceleration limits, and dark surface performance. To read from the registers, read Frame_Period_Upper first followed by Frame_Period_Lower. To write to the registers, write Frame_Period_Lower first followed by Frame_Period_Upper.
38
IC Register State after Reset (power up or setting bit 7, register 0x0a)
Address 0x0 0x01 0x02 Register Product_ID Revision_ID Motion Value 0x02 0xNN 0x00 Meaning Product ID = 2 (Fixed value) Revision of IC (Fixed value). (For each device design revision.) No Motion LED = No Fault No X data overflow No Y data overflow Resolution is 400 counts per inch No X motion No Y motion No image yet to measure No image yet to measure No image yet to measure
0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a
Delta_X Delta_Y SQUAL Average_Pixel Maximum_Pixel Reserved Reserved Configuration_bits
0x00 0x00 0x00 0x00 0x00 -- -- 0x00
Part is not Reset LED Shutter Mode is off No System tests Resolution = 400 counts per inch Pixel Dump is disabled Sleep mode is enabled No data to read No data to read Initial shutter value Initial shutter value Initial frame period value (corresponds to 1500 fps) Initial frame period value (corresponds to 1500 fps)
0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11
Reserved Data_Out_Lower Data_Out_Upper Shutter_Lower Shutter_Upper Frame_Period_Lower Frame_Period_Upper
-- undefined undefined 0x64 0x00 0x20 0xd1
39
Optical Mouse Design References
Application Note AN1179 Eye Safety calculation AN1228
Ordering Information
Specify part number as follows: ADNS-2051 = Sensor IC in a 16-pin staggered DIP, 20 per tube. HDNS-2100 = Round Optical Mouse Lens HDNS-2100#001 = Trimmed Optical Mouse Lens HDNS-2200 = LED Assembly Clip (Black) HDNS-2200#001 = LED Assembly Clip (Clear) HLMP-ED80-XX000 = LED
For product information and a complete list of distributors, please go to our website:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright (c) 2005-2008 Avago Technologies. All rights reserved. Obsoletes 5988-8477EN AV02-1364EN - September 3, 2008

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